The present invention relates in general to power-on reset circuits and, more particularly, to a power-on reset circuit for monitoring a power supply potential and generating a ready signal when the power supply potential reaches a predetermined threshold.
Power-on reset circuits are commonly used in electronic circuit design to indicate when the power supply potential has reached an operational level for an integrated circuit (IC) following system power-up. A typical design approach involves counting a predetermined number of clock cycles after a system reset to allow sufficient time delay for the power supply potential to reach an operational level. The time delay approach can only estimate the slew rate of the power supply potential thus resulting in inefficiency if it allocates too much time for the power supply potential to reach steady-state. Also undesirable is the possibility that using a time delay may allow the IC to begin operating before the power supply potential reaches an adequate level of operation, i.e. not allowing enough time.
Another approach involves coupling the power supply conductor through a parallel resistor-capacitor (RC) combination external to the IC. When the power supply conductor charges the RC time constant to say 3.0 volts, an inverter internal to the IC changes state to indicate the power supply potential is ready for use. One problem with the RC time constant approach is the need for an IC pin to connect to the resistor and capacitor. Furthermore, since the inverter typically changes state before the power supply potential reaches optimum level, the initial behavior of the system is uncertain.
Hence, a need exists for a power-on reset circuit internal to the IC which directly monitors the power supply conductor and issues a ready signal when the power supply potential actually reaches an optimum operational level.